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Current SMIrC Projects

Integrated Impedance Biosensor Arrays

Jon Daniels

There is a need for rapid and inexpensive diagnostic tools for detecting DNA or protein analytes in biological or clinical samples. Impedance biosensors are promising for these applications because they can operate on the sample directly, without a step to label or amplify the target. A probe molecule, which will selectively bind the target analyte, is immobilized to an electrode. When solution containing the target is introduced, target binding will change the electrode-solution impedance slightly. Prior art has utilized expensive impedance analyzers to measure the small impedance changes of a single electrode-solution interface.

We are working towards an integrated measurement platform for a multiplexed impedance biosensor. Our goal is to measure the complex-valued impedance over a range of relatively low frequencies (~100 Hz - 100kHz) on an array of electrodes. A 6x6 array of gold electrodes was designed and fabricated. A homemade impedance measurement setup on a PCB using LabView acquisition demonstrates that the measurement circuit is fundamentally simple. It also allows us to characterize the impedance of our electrode-solution impedance for our particular electrode size and surface chemistry (our probe is DNA or protein attached to a thin polymer). Furthermore, we demonstrated that by using a 2-tone excitation the amount of nonlinearity present in the bias-dependent biological impedance can be quantified without incurring added measurement time; this added information can help discriminate target binding. At present, we are developing an CMOS implementation of the measurement circuit that can be used to simultaneously measure all 36 electrodes. This will include special provisions to accurately measure the amount of nonlinearity along with the small-signal impedance.

Past SMIrC Projects

"Zero-G" Low Power, Low Cost Wireless Transceiver

Shwetabh Verma and Junfeng Xu

Currently, there is an increasing demand for low-cost wireless nodes that consume very little power. For such devices, the difficulty in hardware design comes from design decisions made at the system level. The design of the system is dependent on the application(s) for which the system is being designed. For example, Bluetooth, currently a popular system standard in the wireless industry, aims to remove wires for both voice and data applications which require data rates less than 1 Mbps over distances less than 10 m. Bluetooth-compliant devices currently operate in the 2.45 GHz ISM band. Until now however, the cost of a Bluetooth node that meets its minimum requirements (Class C) is still substantial--not yet low enough for wide consumer acceptance. A major reason for this is that Bluetooth is a system designed to accommodate a wide range of applications. For example, the Bluetooth standard supports synchronous connections due to latency requirements associated with voice traffic. To allow for such flexibility the demands on the hardware are stringent, resulting in high cost.

We propose to design and build the required hardware for a system where cost is our primary concern. This system would support the same data rates over similar distances. We aim to design the system with a hardware perspective, allowing us to make some system-level tradeoffs to ease the circuit design, and hence, minimize cost. Thanks to this degree of freedom, we hope to eliminate most of the expensive off-chip components, and fit the entire circuit (including RF, baseband, and memory) in less than 1 mm˛ of die area, while consuming minimal power.

Optical spatial quantization for higher performance analog to digital conversion

Mona Jarrahi

With rapidly increasing signal bandwidths and the predominance of digital technologies and techniques, there is an increasing need for faster analog-to-digital converters (ADCs) to interface between the analog and digital domains. A competing trend is the increasing need for lower power operation. In conventional ADCs the maximum available power limits the maximum sampling frequency.

We have presented a spatially quantized ADC architecture that achieves mode-locked laser sampling speeds through a fully optical quantization scheme, while extracting the required quantization energy directly from the input analog signal and sampling clock to reduce power consumption. The input voltage is applied to an optical modulator that deflects the sampling pulses from a mode-locked laser onto an array of detectors according to the value of the input voltage.

As a demonstration, the proposed technique was employed in an 8-level quantization proof-of-concept prototype built on GaAs. The prototype consumes only 7.2pJ per conversion step with measurement instrument-limited bandwidth of 18 GHz, projected to an estimated bandwidth of 33 GHz. Measured 8ps full-width half-maximum (FWHM) photodetector output voltages promise the potential of the system to detect a spatially quantized optical pulse train with 125 GS/s repetition rate. To our knowledge, this is the most wideband quantization system reported. Furthermore, the power consumption is an order of magnitude smaller than the predicted power consumption of a traditional system with similar specifications.

DC-DC Conversion for Portable Applications

Michael Mulligan

The recent decade's growth in the handheld consumer electonics industry, coupled with the ever-present demand for increased functionality and lower cost of such devices, is driving a need for low cost, high efficiency power processing units. The current industry standard for generating low voltage power supplies is the synchronous rectifier buck converter (SRBC). However, this power conversion topology suffers from a degraded efficiency at light loads, a problem that can severely limit the battery lifetime of portable devices that spend a substantial amount of time in "stand-by" mode. Additionally, the SRBC requires two off-chip passive filter components. These components greatly increase the overall size and cost of the system.

The goals of this project are to investigate methods for reducing the size and cost of low power, low voltage DC-DC converters for portable applications with a focus towards exploring means of increasing the level of converter integration in standard CMOS technologies.

Optimization of phase-locked loop circuits via geometric programming

David M. Colleran

Feedback Linearization of RF Power Amplifiers

Joel L. Dawson

Improving the performance of the power amplifier is one of the most pressing problems facing designers of modern radio-frequency (RF) transceivers. Linearity and power efficiency of the transmit path are of utmost importance, and the power amplifier has proven to be the bottleneck for both. High linearity enables transmission at the highest data rates for a given channel bandwidth, and power efficiency prolongs battery lifetime in portable units and reduces heat dissipation in high-power transmitters. Cartesian feedback is a power amplifier linearization technique that acts to soften the trade-off between power efficiency and linearity in power amplifiers. Despite its compelling, fundamental advantages, the technique has not enjoyed widespread use because of certain implementation difficulties.

In this work we introduced new techniques for overcoming the challenges faced by the designer of a Cartesian feedback system. The theory of the new techniques was analyzed in detail, and further explored by building a discrete-component prototype. The project's culmination was the first known IC to include a power amplifier and complete Cartesian feedback linearization system on the same die.

Jitter and Phase Noise in Electrical Oscillators

Ali Hajimiri

Wireless and mobile communication has shown a large growth during the last few years. This growth has resulted in stringent requirements on the channel spacing and hence the local oscillators' phase noise. Also, the need for more economical and robust design has resulted in a great thrust toward a system on-chip approach. Providing an on-chip low phase noise local oscillator suitable for today's wireless world has been a major challenge in the field. At the same time, the higher clock frequencies of digital circuits require lower jitter for on-chip oscillators in the clocking circuitry of modern microprocessors. As a result, there is a need for a deeper understanding of the fundamental mechanisms governing the process by which the device, substrate, and supply noise turn into jitter and phase noise.

A new time variant model based on impulse sensitivity functions (ISF) is developed. This model is capable of making quantitative predictions for phase noise and jitter for different types of oscillators. It associates a certain amount of phase noise to every noise source in the circuit. Because of its time variant nature, the model takes into account the effect of cyclostationary noise sources in a natural way. It explains the mechanism for upconversion of low frequency noise sources, such as 1/f noise, and the effect of the rise and fall time symmetry on its upconversion. The theory predicts the jitter due to the correlated and uncorrelated noise sources and the difference in their effects. This approach elucidates several previously unknown design criteria for reducing the phase noise. The model reduces to previously available phase noise models as special cases. The theory is verified experimentally for a large number of oscillators with different topologies.

Optimal Design of CMOS Op-amps via Geometric Programming

Maria del Mar Hershenson

We developed a new method for determining component values and transistor dimensions for CMOS operational amplifiers. A wide variety of design objectives and constraints are posynomial functions of the design variables. As a result the amplifier design problem can be expressed as a special form of optimization problem called geometric programming, for which very efficient global optimization methods have been developed. As a consequence we can efficiently determine globally optimal amplifier designs, or globally optimal tradeoffs among competing performance measures such as power, open-loop gain, and bandwidth. Our method therefore yields completely automated synthesis of (globally) optimal CMOS amplifiers, directly from specifications.

CMOS Global Positioning System Receiver

Derek K. Shaeffer and Arvin Shahani

As CMOS technologies continue to enjoy the benefits of aggressive scaling, they become increasingly attractive for use in radio receivers. We have been pursuing research into the problem of low-power CMOS receiver design. The focus of this work is the implementation of the complete RF and analog sections of a Global Positioning System (GPS) receiver. In particular, we have focused on the low-noise amplifier (LNA) and the on-chip active filter, two blocks that pose special challenges. Theoretical investigations of the LNA problem help to illustrate deficiencies of present-day CMOS models that frustrate the design task. Methods for circumventing those deficiencies have been developed, leading ultimately to a power-constrained optimization of LNA noise performance. Experimentally, this improved theoretical basis has enabled the realization of a 12mW, 1.6GHz, 2.4dB noise figure, differential LNA in a 0.5um CMOS technology.

We have also focused on the power-efficient implementation of active Gm-C filters. Together with the LNA work, these advances have enabled the realization of a 115mW CMOS GPS receiver that includes the complete RF and analog signal path, frequency synthesizer and A/D conversion. The receiver achieves a level of performance that compares favorably with existing commercial solutions in Bipolar and BiCMOS technologies.

Integrated Transceivers for High Data Rate Wireless Communications

Hirad Samavati and Hamid Rategh

The ultimate goal of this project was to design a 5 GHz integrated transceiver using a standard digital CMOS processes. New techniques for fast wireless links between computer terminals were studied. Reducing the cost of such ultra high-speed transceivers was a strong motivation behind this research.

Programmable CMOS Radio Transceiver

Tamara Papalias

Instead of focusing on the commercial aspects, this research focuses on the pedagogical aspects of a communications design. The goal is a single-chip transceiver in standard CMOS. Additionally, many components must be tested separately to enhance student knowledge. The necessary enabling feature is single-poly EPROMs configured as switches.

Superharmonic Injection Locked Oscillators as Low Power Frequency Dividers

Hamid Rategh

Superharmonic injection locking is investigated in a new theoretical approach. In this work we show how an oscillator can be locked to an incident signal whose fundamental frequency equals a harmonic of the oscillator frequency in superharmonic locking, so that the oscillation frequency is an integer fraction of the fundamental frequency of the incident signal. We present a new method to calculate the locking range of an injection locked oscillator both for sub- and super-harmonic locking. We also present a novel oscillator which is locked to half of the incident signal frequency. Low power frequency dividers are designed using injection locked oscillators with cascode transistors.

Wireless Biotelemetry Transmitter

Raphael J. Betancourt

Currently, NASA-Ames Research Center is developing the Life Sciences Advanced BioTelemetry System to conduct space-based animal research. In collaboration with the Fetal Treatment Center at UCSF, NASA is also developing a system for wireless telemetry of physiological parameters of fetuses for monitoring and identifying distress after pre-natal surgery. A low-power highly integrated radio transmitter is key to the success of these project. Our goal is to build a low-power 900MHz RF transceiver suitable for short range biosensor and implantable use.

Modeling and Characterization of On-Chip Transformers

Sunderarajan S. Mohan, C. Patrick Yue, and Maria del Mar Hershenson

We present a scalable analytical model for on-chip transformers that is suitable for design, optimization and circuit simulation. We also provide simple and accurate expressions for evaluating the self inductance and the mutual coupling coefficient (k). The model agrees very well with measurements for a variety of transformer configurations.

50-GHz Interconnect Design in Standard Silicon Technology

Bendik Kleveland

Coplanar waveguides were fabricated in a process that emulates silicon CMOS technologies with 5 to 10 metal layers. The observed S₂₁ loss of 0.3dB/mm at 50 GHz is among the lowest ever reported with standard Al interconnects on Si/SiO₂. Optimum design parameters were counter-intuitive: in some frequency ranges, the lowest loss was achieved with relatively narrow lines over a low-resistivity substrate. This was exploited in the design of transmission lines that are fully compatible with a CMOS technology. The process emulation was calibrated with a commercial 4-layer Al/Cu CMOS technology.

Accumulation-Mode Varactor for RF ICs

Theerachet Soorapanth, C. P. Yue, and Derek Shaeffer

We designed a novel RF IC varactor implemented in standard CMOS process. This device has shown a remarkable tuning range of 150%, sensitivity of 300%/V, and quality factor of 23 at 1 GHz. A physical model of the varactor confirms the measured data. Using the model derived, optimization has shown that a Q as high as 200 can be achieved.

Fractal Capacitors

Hirad Samavati, Ali Hajimiri, and Arvin Shahani

Passive components constitute a major portion of an RF transceiver chip. As a part of this research, a novel way of building inexpensive capacitors is explored. A capacitor element using a fractal structure exploits both lateral and vertical electric field. The structure significantly reduces the area of capacitors, and lowers the parasitic bottom-plate capacitance. Unlike conventional parallel-plate capacitors, the structure enjoys further improvement with the scaling of the process technologies.